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CY7C1444AV25 CY7C1445AV25
36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
Features
* Supports bus operation up to 250 MHz * Available speed grades are 250, 200 and 167 MHz * Registered inputs and outputs for pipelined operation * Optimal for performance (Double-Cycle deselect) * Depth expansion without wait state * 2.5V core power supply * 2.5V/1.8V I/O power supply * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * CY7C1444AV25, CY7C1445AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package * IEEE 1149.1 JTAG-Compatible Boundary Scan * "ZZ" Sleep Mode Option
Functional Description[1]
The CY7C1444AV25/CY7C1445AV25 SRAM integrates 1M x 36/2M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth- expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1444AV25/CY7C1445AV25 operates from a +2.5V core power supply while all outputs operate with a +2.5V or 1.8V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 435 120 200 MHz 3.2 385 120 167 MHz 3.4 335 120 Unit ns mA mA
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05351 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 22, 2006
CY7C1444AV25 CY7C1445AV25
1
Logic Block Diagram - CY7C1444AV25 (1M x 36)
A0,A1,A
ADDRESS REGISTER
2 A[1:0]
MODE ADV CLK
BURST LOGIC
Q1
COUNTER AND
CLR ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQc,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA,DQPA BYTE WRITE REGISTER ENABLE REGISTER
Q0
DQD,DQPD BYTE WRITE DRIVER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER DQA,DQPA BYTE WRITE DRIVER
MEMORY ARRAY SENSE AMPS
BWC
OUTPUT REGISTERS
OUTPUT BUFFERS
E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE GW CE1 CE2 CE3 OE
PIPELINED ENABLE
INPUT REGISTERS
ZZ
2
SLEEP CONTROL
Logic Block Diagram - CY7C1445AV25 (2M x 18)
A0, A1, A
ADDRESS REGISTER
2 A[1:0]
MODE
ADV CLK
Q1 BURST COUNTER AND LOGIC CLR Q0
ADSC ADSP DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS
BWB
OUTPUT REGISTERS
OUTPUT BUFFERS E
DQs, DQPA DQPB
BWA BWE GW CE1 CE2 CE3 OE
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document #: 38-05351 Rev. *E
Page 2 of 26
CY7C1444AV25 CY7C1445AV25
Pin Configurations 100-pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1444AV25 (1M X 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1445AV25 (2M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
MODE A A A A A1 A0 NC/72M A VSS VDD A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC/72M A VSS VDD
Document #: 38-05351 Rev. *E
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 26
CY7C1444AV25 CY7C1445AV25
Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1444AV25 (1M x 36)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC/72M A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW VSS VSS
8
ADSC OE VSS VDD
9
ADV ADSP
10
A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
CY7C1445AV25 (2M x 18)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC/72M A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS `VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05351 Rev. *E
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CY7C1444AV25 CY7C1445AV25
Pin Definitions
Name A0, A1, A I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter.. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the I/O circuitry. Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Page 5 of 26
BWA, BWB BWC, BWD GW
BWE CLK CE1
CE2
CE3
OE
InputAsynchronous
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
ZZ
InputAsynchronous I/OSynchronous
DQs, DQPs
VDD VSS VSSQ VDDQ MODE
Power Supply Ground I/O Ground I/O Power Supply InputStatic
Document #: 38-05351 Rev. *E
CY7C1444AV25 CY7C1445AV25
Pin Definitions (continued)
Name TDO I/O JTAG serial output Synchronous JTAG serial input Synchronous JTAG serial input Synchronous JTAG-Clock - - Description Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die No Connects. Not internally connected to the die. NC/72M, NC/144M,NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1444AV25/CY7C1445AV25 is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1444AV25/CY7C1445AV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1444AV25/CY7C1445AV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired Page 6 of 26
TDI
TMS
TCK NC NC/72M,NC/144M, NC/288M, NC/576M, NC/1G
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1444AV25/CY7C1445AV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the Document #: 38-05351 Rev. *E
CY7C1444AV25 CY7C1445AV25
byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1444AV25/CY7C1445AV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1444AV25/CY7C1445AV25 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1: A0 00 01 10 11 First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Fourth Address A1: A0 11 00 01 10
Linear Burst Address Table (MODE = GND)
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 100 2tCYC Unit mA ns ns ns ns
Document #: 38-05351 Rev. *E
Page 7 of 26
CY7C1444AV25 CY7C1445AV25
Truth Table[2, 3, 4, 5, 6, 7]
Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE OE CLK DQ X X L-H Tri-State X X X X X X X L H H H H H H L L H H H H L L X X X X X L H X L H L H L H X X L H L H X X L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Tri-State Q D Q Q Q D D Q Q D D
L-H Tri-State
L-H Tri-State L-H Tri-State L-H Tri-State
L-H Tri-State L-H Tri-State
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05351 Rev. *E
Page 8 of 26
CY7C1444AV25 CY7C1445AV25
Partial Truth Table for Read/Write[4, 8]
Function (CY7C1444AV25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Truth Table for Read/Write[4, 8]
Function (CY7C1445AV25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
Note: 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05351 Rev. *E
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CY7C1444AV25 CY7C1445AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1444AV25/CY7C1445AV25 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The CY7C1444AV25/CY7C1445AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0 Bypass Register
210
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
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When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit# 89 (for 165-FBGA packages).When this scan cell, called the Document #: 38-05351 Rev. *E Page 11 of 26
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"extest output bus tri-state", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Symbol Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 0 5 5 5 20 20 10 50 20 ns MHz ns ns ns ns ns ns ns Parameter Min. Max. Unit
Output Times
Set-up Times
Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
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2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 2.5V Input rise and fall time..................................................... 1 ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V
1.8V TAP AC Test Conditions
Input pulse levels......................................0.2V to VDDQ - 0.2 Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 0.9V Output reference levels .................................................. 0.9V Test load termination supply voltage .............................. 0.9V
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
1.8V TAP AC Output Load Equivalent
0.9V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 2.5V 0.125V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Test Conditions IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A IOL = 1.0 mA IOL = 100 A VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V 1.7 1.26 -0.3 -0.3 -5 Min. 2.0 2.1 1.6 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.36 5 Max. Unit V V V V V V V V V V A
Note: 11. All voltages referenced to VSS (GND).
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Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1444AV25 000 01011 000110 100111 00000110100 1 CY7C1445AV25 000 01011 000110 010111 00000110100 1 Description Describes the version number Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order (165-ball FBGA package) Bit Size (x18) 3 1 32 89 Bit Size (x36) 3 1 32 89
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. This instruction is 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
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165-ball FBGA Boundary Scan Order[ 12,13]
CY7C1444AV25 (1M x 36), CY7C1445AV25 (2M x 18) Bit # Ball ID Bit # Ball ID 1 26 E11 N6 2 27 D11 N7 3 N10 28 G10 4 P11 29 F10 5 P8 30 E10 6 R8 31 D10 7 R9 32 C11 8 P9 33 A11 9 P10 34 B11 10 R10 35 A10 11 R11 36 B10 12 H11 37 A9 13 N11 38 B9 14 M11 39 C10 15 L11 40 A8 16 K11 41 B8 17 J11 42 A7 18 M10 43 B7 19 L10 44 B6 20 K10 45 A6 21 J10 46 B5 22 H9 47 A5 23 H10 48 A4 24 G11 49 B4 25 F11 50 B3
Notes: 12. Balls which are NC (No Connect) are Pre-Set LOW. 13. Bit# 89 is Pre-Set HIGH.
Bit # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2
Bit # 76 77 78 79 80 81 82 83 84 85 86 87 88 89
Ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +3.6V Supply Voltage on VDDQ Relative to GND ..... -0.5V to + VDD DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V + 5% VDDQ 1.7V to VDD
Electrical Characteristics Over the Operating Range[14, 15]
DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[14] Voltage[14] for 2.5V I/O for 1.8V I/O for 2.5V I/O, IOH = -1.0 mA for 1.8V I/O, IOH = -100 A for 2.5V I/O, IOL = 1.0 mA for 1.8V I/O, IOL= 100 A for 2.5V I/O for 1.8V I/O for 2.5V I/O for 1.8V I/O Input Leakage Current except ZZ and MODE GND VI VDDQ 1.7 1.26 -0.3 -0.3 -5 -30 5 -5 30 -5 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC All speeds 5 435 385 335 185 Test Conditions Min. 2.375 2.375 1.7 2.0 1.6 0.4 0.2 VDD + 0.3V VDD + 0.3V 0.7 0.36 5 Max. 2.625 2.625 1.9 Unit V V V V V V V V V V V A A A A A A mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
ISB2
Automatic CE VDD = Max, Device Deselected, VIN Power-down 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 VDD = Max, Device Deselected, Automatic CE Power-down or VIN 0.3V or Current--CMOS Inputs VIN > VDDQ - 0.3V f = fMAX = 1/tCYC Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0
All speeds
120
mA
ISB3
All speeds
160
mA
ISB4
All Speeds
135
mA
Notes: 14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[16]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD/VDDQ = 2.5V 100 TQFP Max. 6.5 3 5.5 165 FBGA Max. 7 7 6 Unit pF pF pF
Thermal Resistance[16]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 25.21 2.28 165 FBGA Package 20.8 3.2 Unit C/W C/W
AC Test Loads and Waveforms
2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 5 pF R = 1538 VT = 1.25V INCLUDING JIG AND SCOPE R = 1667 VDDQ 10% GND 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns
(a) 1.8V I/O Test Load
OUTPUT Z0 = 50 1.8V
(b)
(c)
R = 14K VDDQ-0.2 10% 5 pF R = 14K GND 1 ns 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
Note: 16. Tested initially and after any design or process change that may affect these parameters.
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Switching Characteristics Over the Operating Range[21, 22]
-250 Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-Up Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z
[18, 19, 20]
-200 Min. 1 5.0 2.0 2.0 2.6 3.2 1.5 1.3 2.6 2.6 3.0 3.0 0 2.6 3.0 0 1.5 1.5 Max. 1 6.0 2.4 2.4
-167 Min. Max. Unit ms ns ns ns 3.4 ns ns ns 3.4 3.4 3.4 ns ns ns ns
Description VDD(Typical) to the first Access Clock Cycle Time Clock HIGH Clock LOW
[17]
Min. 1 4.0 1.5 1.5
Max.
1.0 1.0
Clock to High-Z[18, 19, 20] OE LOW to Output Valid OE LOW to Output Low-Z OE HIGH to Output
[18, 19, 20]
0
High-Z[18, 19, 20]
Notes: 17. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 18. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 19. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. 21. Timing reference level is 1.25V when VDDQ = 2.5V and 0.9V when VDDQ = 1.8V. 22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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Switching Waveforms
Read Cycle Timing[23]
tCYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE,BW
X tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst OE
tOEV t CLZ t OEHZ t OELZ tCO tDOH t CHZ
Data Out (DQ)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURST READ
Burst wraps around to its initial state
DON'T CARE
UNDEFINED
Note: 23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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Switching Waveforms (continued)
Write Cycle Timing[23, 24]
t CYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC extends burst
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BWX
tWES tWEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH
Data in (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE DON'T CARE UNDEFINED
Extended BURST WRITE
Note: 24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
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Switching Waveforms (continued)
Read/Write Cycle Timing[23, 25, 26]
tCYC
CLK
tCH tADS tADH tCL
ADSP
ADSC
tAS tAH
ADDRESS BWE, BWX
A1
A2
A3
tWES tWEH
A4
A5
A6
tCES
tCEH
CE
ADV
OE
tCO tDS tDH tOELZ
Data In (D) Data Out (Q)
High-Z
tCLZ
tOEHZ
D(A3)
D(A5)
D(A6)
High-Z
Q(A1) Back-to-Back READs
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
UNDEFINED
Notes: 25. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 26. GW is HIGH.
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Switching Waveforms (continued)
ZZ Mode Timing[27, 28]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 28. DQs are in high-Z when exiting ZZ sleep mode.
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1444AV25-167AXC CY7C1445AV25-167AXC CY7C1444AV25-167BZC CY7C1445AV25-167BZC CY7C1444AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV25-167BZXC CY7C1444AV25-167AXI CY7C1445AV25-167AXI CY7C1444AV25-167BZI CY7C1445AV25-167BZI CY7C1444AV25-167BZXI CY7C1445AV25-167BZXI 200 CY7C1444AV25-200AXC CY7C1445AV25-200AXC CY7C1444AV25-200BZC CY7C1445AV25-200BZC CY7C1444AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV25-200BZXC CY7C1444AV25-200AXI CY7C1445AV25-200AXI CY7C1444AV25-200BZI CY7C1445AV25-200BZI CY7C1444AV25-200BZXI CY7C1445AV25-200BZXI 250 CY7C1444AV25-250AXC CY7C1445AV25-250AXC CY7C1444AV25-250BZC CY7C1445AV25-250BZC CY7C1444AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV25-250BZXC CY7C1444AV25-250AXI CY7C1445AV25-250AXI CY7C1444AV25-250BZI CY7C1445AV25-250BZI CY7C1444AV25-250BZXI CY7C1445AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 38-05351 Rev. *E
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CY7C1444AV25 CY7C1445AV25
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05351 Rev. *E
0.10
R 0.08 MIN. 0.20 MAX.
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CY7C1444AV25 CY7C1445AV25
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B O0.450.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
PIN 1 CORNER
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.530.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.000.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05351 Rev. *E
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1444AV25 CY7C1445AV25
Document History Page
Document Title: CY7C1444AV25/CY7C1445AV25 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM Document Number: 38-05351 REV. ** *A ECN NO. 124418 254909 Issue Date 03/04/03 See ECN Orig. of Change CGM SYT New data sheet Part number changed from previous revision. New and old part number differ by the letter "A" Modified Functional Block diagrams Modified switching waveforms Added Boundary scan information Added IDD, IX and ISB values in the DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA package Edited Ordering Information typo for 165-ball FBGA part and package name Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical Characteristics table Replaced JA and JC from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Changed IDD from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200 and 167 Mhz respectively Changed ISB1 from 190, 180 and 170 mA to 185 mA for 250, 200 and 167 MHz respectively Changed ISB2 from 80 mA to 100 mA for all frequencies Changed ISB3 from 180, 170 & 160 mA to 160 mA for 250, 200 and 167 MHz respectively Changed ISB4 from 100 mA to 110 mA for all frequencies Changed CIN, CCLK and CI/O from 5, 5 and 7 pF to 6.5, 3 and 5.5 pF respectively for TQFP Package Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz Speed Bin Added lead-free information for 100-pin TQFP and 165 FBGA packages Modified Address Expansion balls in the pinouts for 165 FBGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by Shading and Unshading MPNs as per availability Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed IX current value in MODE from -5 & 30 A to -30 & 5 A respectively and also Changed IX current value in ZZ from -30 & 5 A to -5 & 30 A respectively on page# 16 Modified test condition from VIH < VDD to VIH < VDD Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Description of Change
*B
303533
See ECN
SYT
*C
331778
See ECN
SYT
*D
417509
See ECN
RXU
*E
473229
See ECN
VKN
Document #: 38-05351 Rev. *E
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